Ventana has launched its Veyron V2 RISC-V processor design that’s targeting data center operators and hyperscalers in a bid to help them design their servers with much more precision and on a much faster scale.
Shortly after launching its Veyron V1 chiplets earlier this year, the firm has come out with a successor that can offer an IO hub and accelerators that are partnered with the UCI-Express chiplet connectivity standard to offer 192 cores per socket.
In one conceptual example, six 32-core V2 chiplets were connected with the IO hub through UCI-Express and were augmented with domain-specific acceleration. The IO hub could also connect with memory and components through DDR5 and PCIe 5.0 controllers. However, the firm says organizations can swap out DDR5 controllers for HBM3 controllers if they so choose, according to Next Platform.
Hyperscalers are paying attention to Ventana
The reason Ventana has put out its next generation after launching Veyron V1 only earlier this year is the fact this version used the Bunch of Wires (BoW) standard for interconnecting chiplets – which was the best available at the time.
But Intel then launched the UCI-Express standard in March last year, which proved the superior option for connecting chiplets, and Ventana wasted no time in integrating this technology into the next version of its chip technology.
One of the most promising aspects of this component is benchmarking, with the company’s figures showing the 192-core Veyron 2 RISC-V CPU beating several competitors quite easily on throughput.
These include the 64-core Arm Neoverse V2, 56-core Intel Xeon SPR 8400+, 96-core AMD EPYC Genoa 9654, and 12-core AMD EPYC Bergamo 9754 CPUs.
The Ventana Veyron V2 processor boasted 23% more integer throughout than AMD’s Bergamo CPU, which is one of the fastest processors out there, making this a highly competitive option for businesses.
The base model of the Veyron V2 design comes with four chiplets for 128 cores and eight DDR5 RAM channels, and will enter production in the third quarter of next year. This is because production is relying on the UCI-Express 1.1 PHY standard to become available.
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This post originally appeared on TechToday.